교수 | Department of Semiconductor Engineering

교수

백록현 JA교원

소개

소개
논문/출판/특허
학술활동

학력

2006.03 ~ 2011.02 포항공과대학교 (박사-반도체소자/회로)
2004.03 ~ 2006.02 포항공과대학교 (석사-반도체소자/회로)
2000.03 ~ 2004.02 고려대학교 (학사-전기전자전파)

주요경력

2015.08 ~ 2017.01 삼성전자반도체연구소 LOGIC TD팀
2011.04 ~ 2015.06 SEMATECH

전문분야

차세대 로직 소자: GAA Nanosheet/Forksheet/CFET + Backside PDN
차세대 메모리 소자: 3D-NAND/HBF/3D-DRAM/IGZO channel
Reliability: HZO/leakage/HCI/TDDB/BTI
AI 기반: 소자 개발/Biasing 최적화/수명 예측/산포 분석/Compact Modeling
공정: gatestack(HZO/IGZO)/silicide/thermal process

학술지

■국제전문학술지■
CurrentVoltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning, IEEE Access, , 12, 23881-23886 (2024 )
Analysis of Mechanical Stress on FowlerNordheim Tunneling for Program Operation in 3D NAND Flash Memory, SolidState Electronics, , 216, - (2024 )
BCl3Cl2 plasma etching process to fabricate a ferroelectric gate structure for device integration, SolidState Electronics, , 216, - (2024 )
Accurate Evaluation of ElectroThermal Performance in Silicon Nanosheet FieldEffect Transistors with Schemes for Controlling Parasitic Bottom Transistors, Nanomaterials, , 14, - (2024 )
Novel Trench InnerSpacer Scheme to Eliminate Parasitic Bottom Transistors in Silicon Nanosheet FETs vol 70 pg 396 2023, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 71, 4437-4437 (2024 )
FEOL Monolithic CoIntegration of FeFET and CMOS on 8Inch Wafer Using Laser Spike Annealing With Implementation of an FeFET Inverter, IEEE ACCESS, , 12, 110273-110282 (2024 )
Impact of Process Sequence and Device Architecture on Mechanical Stress and Electrical Properties of 3D Nand Flash, IEEE Transactions on Electron Devices, , 71, 5354-5360 (2024 )
Channel Trimming Process to Improve ElectroThermal Characteristics for Sub3nm Node Si Nanosheet FETs, IEEE Transactions on Electron Devices, , 71, 7184-7191 (2024 )
Neural NetworkBased prediction for CrossTemperature induced VT distribution shift in 3D NAND flash memory, SolidState Electronics, , 217, - (2024 )
Machine LearningDriven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley ShortChannel InsulatedGate FieldEffect Transistor ModelCommon Multigate for Multidevice Applications, Advanced Intelligent Systems, , , - (2024 )
MultiTask Learning for RealTime BSIMCMG Parameter Extraction of NSFETs with Multiple Structural Variations, IEEE Access, , 12, 184619-184628 (2024 )
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring, Advanced Intelligent Systems, , 6, - (2024 )
BSPDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node, IEEE Transactions on Electron Devices, , 71, 4028-4032 (2024 )
Quantitative analysis of irregular channel shape effects on chargetrapping efficiency using massive 3D NAND data, Materials Science in Semiconductor Processing, , 157, - (2023 )
Novel Trench InnerSpacer Scheme to Eliminate Parasitic Bottom Transistors in Silicon Nanosheet FETs, IEEE Transactions on Electron Devices, , , - (2023 )
H2 Plasma and PMA Effects on PEALDAl2O3 Films with Different O2 Plasma Exposure Times for CIS Passivation Layers, Nanomaterials, , 13, 731- (2023 )
Improved ISPP scheme for narrow threshold voltage distribution in 3D NAND flash memory, SolidState Electronics, , 202, 108607- (2023 )
Novel HighSpeed Ternary Logic Using StepShaped Threshold Switch, IEEE Electron Device Letters, , 44, 368-371 (2023 )
Holistic Optimization of Trap Distribution for PerformanceReliability in 3D NAND Flash Using Machine Learning, IEEE Access, , 11, 7135-7144 (2023 )
A Novel SourceDrain Extension Scheme with LaserSpike Annealing for Nanosheet FieldEffect Transistors in 3D ICs, Nanomaterials, , 13, - (2023 )
Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps, Nanomaterials, , 13, - (2023 )
Curing Process on Passivation Layer for BacksideIlluminated CMOS Image Sensor Application, IEEE Access, , 11, 60660-60667 (2023 )
Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development, Advanced Intelligent Systems, , 5, - (2023 )
Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3D NAND Flash Memory, IEEE Transactions on Electron Devices, , 70, 6313-6317 (2023 )
Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub3nm Node, IEEE Transactions on Electron Devices, , 70, 6132-6137 (2023 )
Modeling of 3D NAND Characteristics for Cross‐Temperature by Using Graph Neural Network and Its Application, Advanced Intelligent Systems, , 5, - (2023 )
Novel Scheme of Inner Spacer Length Optimization for Sub3nm Node Silicon np Nanosheet FieldEffect Transistors, IEEE Transactions on Electron Devices, , 70, 6151-6156 (2023 )
Performance Power and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail, IEEE Transactions on Electron Devices, , 69, 894-899 (2022 )
DC Performance Variations by Grain Boundary in SourceDrain Epitaxy of Sub3nm Nanosheet FieldEffect Transistors, IEEE ACCESS, , 10, 22032-22037 (2022 )
Effect of hydrogen plasma treatment on the electrical properties for SiCbased power MOSFETs, Microelectronic Engineering, , 258, - (2022 )
Extraction of Device Structural Parameters Through DCAC Performance Using an MLP Neural Network Algorithm, IEEE Access, , 10, 64408-64419 (2022 )
BiDirectional Long ShortTerm Memory Neural Network Modeling of Data Retention Characterization in 3D TripleLevel Cell NAND Flash Memory, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 69, 4241-4247 (2022 )
Channel Thickness and Grain Size Engineering for Improvement of Variability and Performance in 3D NAND Flash Memory, IEEE Transactions on Electron Devices, , 69, 3681-3687 (2022 )
Novel Modeling Approach to Analyze Threshold Voltage Variability in Short GateLength 15–22 nm Nanowire FETs with Various Channel Diameters, Nanomaterials, , 12, - (2022 )
Curing defects in plasmaenhanced atomic layer deposition of Al2O3 by six methods, Materials Science in Semiconductor Processing, , 152, - (2022 )
Sensitivity of Inner Spacer Thickness Variations for Sub3nm Node Silicon Nanosheet FieldEffect Transistors, NANOMATERIALS, , 12, - (2022 )
LearningBased Ordering Characters on Ancient Document, COMPUTATIONAL INTELLIGENCE AND NEUROSCIENCE, , 2022, - (2022 )
Electrical Coupling Effect of Forksheet FET for Power Performance and Area Analysis, IEEE Transactions on Electron Devices, , 69, 7096-7101 (2022 )
Nanowire Diameter Dependency of the Variability in np Silicon Nanowire FETs With Ultrashort Gate Length of 15 nm, IEEE Transactions on Electron Devices, , 69, 6529-6534 (2022 )
A Review of MultiModal Learning from the TextGuided Visual Processing Viewpoint, Sensors, , 22, 6816- (2022 )
Arbitrary Font Generation by Encoder Learning of Disentangled Features, Sensors, , 22, 2374- (2022 )
Analysis of TSVInduced Mechanical Stress and Electrical Noise Coupling in Sub 5nm Node Nanosheet FETs for Heterogeneous 3DICs, IEEE Access, , 9, 16728-16735 (2021 )
Origin of Incremental Step Pulse Programming ISPP slope degradation in charge trap nitride based multilayer 3D NAND flash, SOLIDSTATE ELECTRONICS, , 175, - (2021 )
DigitalAnalog Performance Optimization of Vertical Nanowire FETs Using Machine Learning, IEEE ACCESS, , 9, 29071-29077 (2021 )
TCADBased Flexible Fin Pitch Design for 3nm Node 6TSRAM Using Practical SourceDrain Patterning Scheme, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 68, 1031-1036 (2021 )
Demonstration of TiO2 Based Ultra Highk k 30 MetalInsulator–Semiconductor Capacitor and Its Electrical Properties, Journal of Nanoscience and Nanotechnology, , 21, 4394-4399 (2021 )
Monolithic 3D 6TSRAM Based on Newly Designed Gate and SourceDrain Bottom Contact Schemes, IEEE ACCESS, , 9, 138192-138199 (2021 )
Observation of mobility and velocity behaviors in ultrascaled LG15 nm silicon nanowire fieldeffect transistors with different channel diameters, SOLIDSTATE ELECTRONICS, , 164, - (2020 )
Threshold Voltage Variations Induced by Si1xGex and Si1xCx of Sub 5nm Node Silicon Nanosheet FieldEffect Transistors, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, , 20, 4684-4689 (2020 )
Sensitivity of SourceDrain Critical Dimension Variations for Sub5nm Node Fin and Nanosheet FETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 67, 258-262 (2020 )
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5nm Node SoC Application, IEEE ACCESS, , 8, 35873-35881 (2020 )
Improved LongTerm Responses of AuDecorated Si Nanowire FET Sensor for NH3 Detection, IEEE SENSORS JOURNAL, , 20, 2270-2277 (2020 )
Reduction of Process Variations for Sub5nm Node Fin and Nanosheet FETs Using Novel Process Scheme, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 67, 2732-2737 (2020 )
Neural Approach for Modeling and Optimizing SiMOSFET Manufacturing, IEEE ACCESS, , 8, 159351-159370 (2020 )
Neural Network Based Design Optimization of 14nm Node FullyDepleted SOI FET for SoC and 3DIC Applications, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, , 8, 1272-1280 (2020 )
Device Design Guideline of 5nmNode FinFETs and Nanosheet FETs for AnalogRF Applications, IEEE ACCESS, , 8, 189395-189403 (2020 )
A Novel Sub5nm Node DualWorkfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications, IEEE ACCESS, , 8, 196975-196978 (2020 )
Metal SourceDrainInduced Performance Boosting of Sub7nm Node Nanosheet FETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 66, 1868-1873 (2019 )
Optimization of nanosheet number and width of multistacked nanosheet FETs for sub7nm node system on chip applications, JAPANESE JOURNAL OF APPLIED PHYSICS, , 58, - (2019 )
PunchThroughStopper Free Nanosheet FETs With Crescent InnerSpacer and Isolated SourceDrain, IEEE ACCESS, , 7, 38593-38596 (2019 )
Bottom oxide Bulk FinFETs Without PunchThroughStopper for Extending Toward 5nm Node, IEEE ACCESS, , 7, 75762-75767 (2019 )
Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films, Journal of Materials Chemistry A, , 7, 25838-25844 (2019 )
SourceDrain Patterning FinFETs as Solution for Physical Area Scaling Toward 5nm Node, IEEE ACCESS, , 7, 172290-172295 (2019 )
Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical siliconoxidenitrideoxidesilicon SONOS NAND flash memory, JAPANESE JOURNAL OF APPLIED PHYSICS, , 57, - (2018 )
Systematic analysis of oxide trap distribution of 4HSiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior, SOLIDSTATE ELECTRONICS, , 140, 18-22 (2018 )
Analog FigureofMerits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between InversionMode and Junctionless Nanowire FETs, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, , 18, 6598-6601 (2018 )
Study on Random Dopant Fluctuation in CoreShell Tunneling FieldEffect Transistors, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 65, 3131-3135 (2018 )
MultiVth Strategies of 7nm node Nanosheet FETs With Limited Nanosheet Spacing, IEEE Journal of the Electron Devices Society, , 6, 861-865 (2018 )
Impact of geometrical parameters on the electrical performance of networkchannel polycrystalline silicon thinfilm transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, , 57, - (2018 )
Systematic DCAC Performance Benchmarking of Sub7nm Node FinFETs and Nanosheet FETs, IEEE Journal of the Electron Devices Society, , 6, 942-947 (2018 )
Work function consideration in vacuum field emission transistor design, JOURNAL OF VACUUM SCIENCE amp TECHNOLOGY B, , 35, - (2017 )
HighPerformance Logic Transistor DC Benchmarking Toward 7 nm TechnologyNode Between IIIV and Si Trigate nMOSFETs Using VirtualSource Injection Velocity Model, SOLIDSTATE ELECTRONICS, , 116, 100-103 (2016 )
ProcessInduced Variations of 10nm Node Bulk nFinFETs Considering MiddleofLine Parasitics, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 63, 3399-3405 (2016 )
Junction Design Strategy for Si Bulk FinFETs for SystemonChip Applications Down to the 7nm Node, IEEE ELECTRON DEVICE LETTERS, , 36, 994-996 (2015 )
Investigation of RC Parasitics Considering MiddleoftheLine in SiBulk FinFETs for Sub14nm Node Logic Applications, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 62, 3441-3444 (2015 )
Impact of Spacer Dielectric Constant on Parasitic RC and Design Guidelines to Optimize DCAC Performance in 10 nm Node SiNanowire FETs, JAPANESE JOURNAL OF APPLIED PHYSICS, , 54, 4DN08-1-4DN08-5 (2015 )
Physical DC and Thermal Noise Models of 18 nm DoubleGate Junctionless pMOSFETs for Low Noise RF Applications, JAPANESE JOURNAL OF APPLIED PHYSICS, , 54, 4DC08-1-4DC08-6 (2015 )
Investigation of ProcessInduced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETs, SOLIDSTATE ELECTRONICS, , 96, 27-33 (2014 )
STLM A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity, IEEE ELECTRON DEVICE LETTERS, , 34, 1082-1084 (2013 )
Device Design Guidelines for Nanoscale FinFETs in RFAnalog Applications, IEEE ELECTRON DEVICE LETTERS, , 33, 1234-1236 (2012 )
Electrical characteristics of 20nm junctionless Si nanowire transistors, SOLIDSTATE ELECTRONICS, , 73, 7-10 (2012 )
Characterization and Modeling of 1f Noise in Sinanowire FETs Effects of Cylindrical Geometry and Different Processing of Oxides, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 10, 417-423 (2011 )
CV Characteristics in Undoped GateAllAround Nanowire FET Array, IEEE ELECTRON DEVICE LETTERS, , 32, 116-118 (2011 )
A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2HfO2 Gate Stack nMOSFETs, MICROELECTRONIC ENGINEERING, , 88, 3411-3414 (2011 )
Comparison of Series Resistance and Mobility Degradation Extracted from nand pType SiNanowire Field Effect Transistors Using the YFunction Technique, JAPANESE JOURNAL OF APPLIED PHYSICS, , 49, 4DN06-01-4DN06-05 (2010 )
Characteristics of the Series Resistance Extracted from Si Nanowire FETs Using the YFunction Technique, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 9, 212-217 (2010 )
A new physical 1f noise model for double stack highk gate dielectric MOSFETs, IEEE ELECTRON DEVICE LETTERS, , 30, 1365-1367 (2009 )
LowFrequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric, IEEE ELECTRON DEVICE LETTERS, , 30, 523-525 (2009 )
A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 Gate Stack nMOSFETs, MICROELECTRONIC ENGINEERING, , 88, 3411-3414 (2009 )
Lowtemperature performance of nanoscale MOSFET for deepspace RF applications, IEEE ELECTRON DEVICE LETTERS, , 29, 775-777 (2008 )
Optimization of Asymmetries in SourceDrain Configurations and Tapered Channels for VerticalTransport Silicon Nanosheet FETs, IEEE Transactions on Electron Devices, , , - (0020 )

학술회의 논문

Improving Program Efficiency of 3D NAND Cell Structure Based on Artificial Neural Network, , 0, 0, - (2021)
Si GateAllAround Nanosheet FET the Key Enabler of 3nm Technology Node, 제 28회 반도체학술대회, 0, 0, - (2021)
Neural Network Based 14nm Node FullyDepleted FET Design for AC Applications of SoC and 3DIC, The 18th International Nanotech Symposium Exhibition, 0, 0, - (2020)
Electrical and Dielectric Properties of TiO2 Based MIS Capacitor, The 18th International Nanotech Symposium Exhibition, 0, 0, - (2020)
TSVtoTransistor Noise Coupling Characterizations for Sub 5nm Node Fin and Nanosheet FETs in 3DIC, The 18th International Nanotech Symposium Exhibition, 0, 0, - (2020)
Interface trap curing effects on highk gate stack AlAl2O3Sisub by rapid thermal anneal RTA, The 18th International Nanotech Symposium Exhibition, 0, 0, - (2020)
SRAM Performance Variations Induced by SourceDrain Mole Fraction Change of Sub 5nm Node Silicon Nanosheet FieldEffect Transistors, The 18th International Nanotech Symposium Exhibition, 0, 0, - (2020)
Neural Network Based Design Optimization of 14nm Node FullyDepleted SOI FET for SoC and 3DIC applications, 4th IEEE Electron Devices Technology and Manufacturing EDTM Conference 2020, 0, 0, - (2020)
Defect Curing Effects on Highk Gate Stack AlAl2O3Sisub by Using H2 Plasma Treatment and Rapid Thermal Anneal, 제 27회 반도체학술대회, 0, 0, - (2020)
Power Performance and Area Analysis of SourceDrain Patterning np FinFETs based 6TSRAM cell for 3nm technology node, 제 27회 반도체학술대회, 0, 0, - (2020)
Demonstration of TiO2 based ultra highk k30 MIS capacitor and its electrical properties, 제 27회 반도체학술대회, 0, 0, - (2020)
The Origin of Incremental Step Pulse Programming ISPP Slope Degradation in NAND Flash Memory, 제 27회 반도체학술대회, 0, 0, - (2020)
Scalability of OTS Integrated PCM for 3D Stackable Crosspoint Array Structure Using TCAD Simulation, the 17th International Nanotech Symposium Exhibition, 0, 0, - (2019)
Comparison of virtual source velocity and apparent mobility in shrunk Lg15 nm npSNWFETs with various channel diameters, the 17th International Nanotech Symposium Exhibition, 0, 0, - (2019)
Extensive Analysis of Incremental Step Programming Pulse ISPP Slope Degradation in NAND Flash Memory, the 17th International Nanotech Symposium Exhibition, 0, 0, - (2019)
Impact of ThermoMechanical Stress Induced by ThroughSilicon Vias on Performance Variations of 5nm Node SiNanosheet FETs, the 17th International Nanotech Symposium Exhibition, 0, 0, - (2019)
Critical dimension variations of sub 5nm node fin and nanosheet FETs, the 17th International Nanotech Symposium Exhibition, 0, 0, - (2019)
The Effects of Realistic Ushaped SourceDrain on DCAC Performances of Silicon Nanosheet FETs for Sub 5nm Node SoC Applications, 2019 IEEE Electron Devices Technology and Manufacturing Conference EDTM, 0, 0, 133-135 (2019)
Observation of Mobility and Velocity Behaviors in Ultra Scaled Lg15 nm Silicon Nanowire pMOSFETs with Different Channel Diameters, 제26회 한국반도체학술대회, 0, 0, - (2019)
Vth Variation Induced by SD Mole Fraction and SiSiGe Intermixing of SiNSFETs, 제26회 한국반도체학술대회, 0, 0, - (2019)
Observation of Mobility and Velocity as Channel Diameter Change in the Shrunk Lg 18nm Silicon Nanowire MOSFETs, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
Design Strategy of 20nm node single PRAM cell based on TCAD Simulation, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
Geometric Optimization of Silicon GateAllAround FieldEffect Transistors GAAFETs for DCAC Performances, 제1회 반도체공학회 학술대회, 0, 0, - (2018)
Nanosheet Number and Width Optimization of Multi Stacked NanoSheet FET for 7nm Node SoC Application, Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials, 0, 0, 877-878 (2018)
Vth variation of string SONOS NAND Flash depending on single grain boundary and stored electron charges in an adjacent cell, Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials, 0, 0, 793-794 (2017)
Improving DMMP Salin simulant Sensing Characteristics of TFQ Functionalized Graphene Chemiresistive Sensors, Proceedings of the 17th IEEE international Conference on Nanotechnology, 0, 0, 675-677 (2017)
HighPerformance IIIV Devices for Future Logic Applications, ELECTRON DEVICES MEETING IEDM 2014 IEEE INTERNATIONAL, 0, 0, - (2014)
Physical DC and Thermal Noise Models of 18 nm DG Junctionless pMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2014)
Impact of Highk Spacers on Parasitic Effects Considering DCAC Performance Optimization in SiNanowire FETs for sub 10 nm Technology Node, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2014)
Electrostatics and Performance Benchmarking using all Types of IIIV MultiGate FinFETs for sub 7nm Technology Node Logic Application, INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST, 0, 0, - (2014)
Sub100 nm InGaAs QuantumWell QW MOSFETs with Al2O3HfO2 EOT 1 nm for LowPower Logic Applications, ELECTRON DEVICES MEETING IEDM 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
Comprehensive Layout and Process Optimization Study of Si and IIIV Technology for sub7nm Node, ELECTRON DEVICES MEETING IEDM 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
VLSI Processed InGaAs on Si MOSFETs with Thermally Stable SelfAligned NiInGaAs Contacts Achieving Enhanced Drive Current and Pathway Towards a Unified SD Contact Module, ELECTRON DEVICES MEETING IEDM 2013 IEEE INTERNATIONAL, 0, 0, - (2013)
Extraction of Series Resistance on Junctionless and Inversionmode nanowire FET through the Method based on Yfunction, INTERNATIONAL CONFERENCE ON DEVICE RESEARCH CONFERENCE, 0, 0, - (2013)
Effects of Layout and Process Parameters on DeviceCircuit Performance and Variability for 10nm Node FinFET Technology, INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST, 0, 0, - (2013)
Effects of fin height of tapered FinFETs on the sub22nm System on Chip SoC application using TCAD simulation, INTERNATIONAL SYMPOSIUM ON VLSITSA, 0, 0, - (2013)
Modeling and Analysis of the Parasitic Series Resistance in Raised SourceDrain FinFETs with Polygonal Shaped Epitaxy, INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 0, 0, - (2012)
Comprehensive Study of ProcessInduced Device Performance Variability and its Optimization for 14 nm Technology Node Bulk FinFETs, INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 0, 0, - (2012)
Conformal lowdamage shallow junction technology Xj5nm with optimized contacts for FinFETs as a Solution Beyond 14nm Node, INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY, 0, 0, - (2012)
Comparative Study of Geometrydependent Capacitances of Planar FETs and DoubleGate FinFETs Optimization and Process Variation, INTERNATIONAL SYMPOSIUM ON VLSITSA, 0, 0, - (2012)
Reliable Extraction of Series Resistance in Silicon Nanowire FETs Using Yfunction Technique, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2011)
Analysis of Bottom Channel Effect in Silicon Nanowire FET based on BulkSilicon Reduction of Parasitic Capacitance caused by SiGe layer, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2011)
Analysis of Parasitic Bottom Capacitance in n and ptype SiNanowire Field Effect Transistors on Bulk, IEEENANO, 0, 0, - (2011)
Investigation of GIDL Behavior in SiNanowire FET with Hot Carrier Stress, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS한국반도체학술대회, 0, 0, - (2011)
Characteristics and Modeling of Sinanowire FETs Invited paper, IEEE INTERNATIONAL CONFERENCE ON SOLIDSTATE AND INTEGRATED CIRCUIT TECHNOLOGY, 0, 0, - (2010)
Comparative Study of CV Characteristics in SiNWFET and MOSFET Invited paper, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2010)
CV Characteristics and Analysis of Undoped GateAllAround Nanowire FET Array, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, 1277-1278 (2010)
LowFrequency Noise Behavior of LaDoped HfBased Dielectric nMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2010)
Low‐Frequency Noise Analysis in HfO2HfO2SiON Gate Stack nMOSFETs with Different Interfacial Layer Thickness, INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, 0, 0, - (2010)
GIDL analysis of underlap double gate MOSFET with variable channel thickness and doping using quantum simulation, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK SUMMER CONFERENCE, 0, 0, - (2010)
Comparative study on device performance of Junctionless doublegate MOSFET, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK SUMMER CONFERENCE, 0, 0, - (2010)
Characteristics of GateAllAround SiNWFET including Rsd Cylindrical Coordinate Based 1f Noise and Hot Carrier Effects, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2010)
Accurate Extraction of Volume Trap Density from SiNanowire FET using the Newly Developed Cylindrical Coordinate Based 1f noise model, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS한국반도체학술대회, 0, 0, - (2010)
Impact of Dipoleinduced Dielectric Relaxation on Highfrequency Performance in Laincorporated HfSiONMetal Gate nMOSFET, ELECTRON DEVICES MEETING IEDM 2009 IEEE INTERNATIONAL, 0, 0, - (2009)
Hot Electron Degradation Effects in 35nm InAlAsInGaAs Metamorphic HEMT, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK FALL CONFERENCE, 0, 0, - (2009)
Fabrication DC and Low Frequency Noise Characteristics of Silicon Nanowire FET, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK FALL CONFERENCE, 0, 0, - (2009)
Series Resistance Behavior Extracted from Silicon Nanowire Transistors Using the Yfunction Technique, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, 1108-1109 (2009)
RF performance degradation in 100nm metal gatehighk dielectric nMOSFET by hot carrier effects, SOLID STATE DEVICE RESEARCH CONFERENCE 2009 ESSDERC 09 PROCEEDINGS OF THE EUROPEAN, 0, 0, - (2009)
RF degradation of short channel metal gatehighk dielectric nMOSFET by hot carrier effect, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK SUMMER CONFERENCE, 0, 0, - (2009)
High Pressure Hydrogen Annealing Effect of CESL Nitride Stressor MOSFETs with Metal GateHighk Dielectric on the Performance and Reliability, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2009)
Effects of High Pressure Hydrogen Anneal Process on Performance and Reliability in HfO2SiO2 Dielectric with Contact Etch Stop Layer Stressor, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2009)
Reliability of HfO2SiO2 Dielectric with Strain Engineering using CESL Stressor, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2009)
RF and Hot Carrier Effects in metal gatehighk Dielectric nMOSFETs at cryogenic temperature, IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 0, 0, - (2009)
RF characteristics in Metal GateHighK Dielectric nMOSFETs at cryogenic temperature, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS한국반도체학술대회, 0, 0, - (2009)
DC and Reliability Characteristics of 45nm Node MOSFETs with using HfSiONTiN Gate Stacks, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS한국반도체학술대회, 0, 0, - (2009)
Effective Mobility Extraction of the Advanced MOSFETs Using RF Modeling, PROCEEDINGS OF THE KOREAN CONFERENCE ON SEMICONDUCTORS한국반도체학술대회, 0, 0, - (2009)
Effective Carrier Mobility Extraction Based on RF Modeling for Highly Leaky MOSFET Devices with Short Channel Length and Small Area, SPANISH CONFERENCE ON ELECTRON DEVICES, 0, 0, - (2009)
Novel Extrinsic Series Resistance Extraction Methodology for Nanoscale MOSFETs, IEEE INTERNATIONAL RF AND MICROWAVE CONFERENCE, 0, 0, - (2008)
A Novel Seriesresistance Extraction Method for Nanoscaled nMOSFETs Considering Mobility Degradation due to Vbs, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
Reliability of HfO2SiO2 Dielectric with Strain Engineering using CESL Stressor, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
GateInduced Drain Leakage GIDL Performance of Strain Engineering using CESL Stressor with Highk gate dielectric, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
Effective Mobility Extraction Methodology Using RF Modeling Scheme for Leaky MOSFET with Short Channel Length and Small Area, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
Temperature dependent performances of nMOSFET with HfLaSiO gate dielectric, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
The Performance of HfSiONTiN Gate Stack MOSFETs for 45 nm Node LSTP Application Using Conventional Fabrication Process, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2008)
Comparison of PECVD and RTCVD CESL Nitride Stressor in Reliability and Performance Improvement for HighkMetal Gate CMOSFETs, INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, 0, 0, - (2008)
IV modeling for nanoscale nMOSFET from liquidnitrogen temperature to room temperature, IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE, 0, 0, - (2006)
70nm CMOS BSIM4 Macro modeling for RFIC design, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK SUMMER CONFERENCE, 0, 0, - (2006)
Optimized scalable IV Modeling for 70nm Gate length NanoCMOS using BSIM4, PROCEEDINGS OF SEMICONDUCTOR SOCIETY IEEK SUMMER CONFERENCE, 0, 0, - (2005)

IP

백록현,이상욱, 반도체 장치 및 이의 제조 방법, 한국, 10-2024-0143791 (P202)
백록현,이상욱, 반도체 장치 및 이의 제조 방법, -, PCT/KR2025/0000 (P202)
백록현,윤혁,김충기,한성주,변홍철,유민수, 반도체 소자 성능에 대한 공정의 영향 평가 방법 및 장치와 이들의 적용, USA, 18/987,848 (P202)
백록현,조경래,최현철,이정식, 그래프 신경망 기반의 메모리의 셀 단위 분석 방법 및 이를 수행하기 위한 컴퓨팅 장치, USA, 18/622,741 (P202)
백록현,윤혁,안창현,최현철, 반도체 공정 최적화를 위한 학습 방법 및 이를 수행하기 위한 컴퓨팅 장치, USA, 18/814,380 (P202)
백록현,남기훈, 프로그램 교란 억제를 위한 메모리 장치 및 그것의 프로그램 방법, 한국, 10-2023-0178740 (P202)
백록현,남기훈, 프로그램 교란 억제를 위한 메모리 장치 및 그것의 프로그램 방법, USA, 18/814,030 (P202)
백록현,남기훈, 프로그램 교란 억제를 위한 메모리 장치 및 그것의 프로그램 방법, 중국, 202411165594.1 (P202)
백록현,이상욱, 축소된 소자 간격을 가지는 반도체 구조 및 이의 제조방법, 한국, 10-2024-0039373 (IP24)
백록현,윤혁,김충기,한성주,변홍철,유민수, 반도체 소자 성능에 대한 공정의 영향 평가 방법 및 장치와 이들의 적용, 한국, 10-2023-0187638 (IP23)
백록현,조경래,최현철,이정식, 그래프 신경망 기반의 메모리의 셀 단위 분석 방법 및 이를 수행하기 위한 컴퓨팅 장치, 한국, 10-2023-0149979 (2023)
백록현,남기훈, 3차원 낸드플래시 메모리의 프로그램 교란 억제를 위한 프로그램 동작 방법, 한국, 10-2023-0111519 (2023)
백록현,윤혁,안창현,최현철, 반도체 공정 최적화를 위한 학습 방법 및 이를 수행하기 위한 컴퓨팅 장치, 한국, 10-2023-0144301 (2023)
백록현,윤혁, 반도체 소자 제조 파라미터 설정 방법 및 장치, USA, 18/458,896 (2023)
백록현,이상욱, 확장된 소스/드레인을 가지는 게이트-올-어라운드 전계효과 트랜지스터, USA, 18/367,854 (2023)
백록현,이상욱, 확장된 소스/드레인을 가지는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조 방법, 한국, 10-2023-0083347 (2023)
백록현,이상욱, 확장된 소스/드레인을 가지는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조 방법, 한국, 10-2023-0021300 (2023)
백록현,정진수, 트랜치 내부 스페이서를 갖는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조방법, 대만, 112100887 (2023)
백록현,정진수, 트랜치 내부 스페이서를 갖는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조방법, -, PCT/KR2022/0217 (2023)
백록현,정진수, 트랜치 내부 스페이서를 갖는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2022-0190897 (2023)
백록현,정진수, 트랜치 내부 스페이서를 가지는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조 방법, 한국, 10-2022-0165880 (2022)
백록현,정진수,윤준식, 트랜치 내부 스페이서를 갖는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조방법, 대만, 111146434 (2022)
백록현,윤준식,정진수,이승환, 축소된 소스/드레인 에피텍셜 구조를 갖는 전계효과 트랜지스터의 제조방법, USA, 18/071,876 (2022)
백록현,윤준식,정진수,이승환, 축소된 소스/드레인 에피텍셜 구조를 갖는 전계효과 트랜지스터의 제조방법, USA, 18/071,876 (2022)
백록현,윤혁, 반도체 소자 제조 파라미터 설정 방법 및 장치, 한국, 10-2022-0116011 (2022)
백록현,윤혁, 반도체 파라미터 설정 장치 및 방법, USA, 17/983,319 (2022)
백록현,윤준식,정진수, 트랜치 내부 스페이서를 갖는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조방법, -, PCT/KR2022/0068 (2022)
백록현,윤준식,윤혁,최현철, 반도체 제조 파라미터 설정 방법 및 이를 수행하기 위한 컴퓨팅 장치, USA, 17/551,450 (2022)
백록현,윤혁, 반도체 파라미터 설정 장치 및 방법, 한국, 10-2022-0025392 (2022)
백록현,정진수,윤준식, 트랜치 내부 스페이서를 가지는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조 방법, 한국, 10-2021-0108414 (2021)
백록현,정진수,윤준식, 트랜치 내부 스페이서를 가지는 게이트-올-어라운드 전계효과 트랜지스터 및 이의 제조 방법, 한국, 10-2021-0108414 (2021)
백록현,이준종,윤준식, 모놀리식 삼차원 집적회로 디바이스 및 이의 제조방법, 한국, 10-2021-0110079 (2021)
백록현,이준종,윤준식, 모놀리식 삼차원 집적회로 디바이스 및 이의 제조방법, 한국, 10-2021-0110079 (2021)
백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, USA, 17/387,876 (2021)
백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, USA, 17/387,876 (2021)
백록현,윤준식,최현철,윤혁, 반도체 제조 파라미터 설정 방법 및 이를 수행하기 위한 컴퓨팅 장치, 한국, 10-2020-0133780 (2020)
백록현,윤준식,최현철,윤혁, 반도체 제조 파라미터 설정 방법 및 이를 수행하기 위한 컴퓨팅 장치, 한국, 10-2020-0133780 (2020)
백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, 한국, 10-2020-0116933 (2020)
백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, 한국, 10-2020-0116933 (2020)
백록현,윤준식, 단일 구조의 캐스코드 소자 및 이의 제조방법, 한국, 10-2020-0116933 (2020)
백록현,윤준식,정진수,이승환, 소스/드레인 에피 크기를 조절할 수 있는 전계효과 트랜지스터 및 이의 제조방법, USA, 16/898,706 (2020)
백록현,윤준식,정진수,이승환, 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법, USA, 16/898,706 (2020)
백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, USA, 16/750,292 (2020)
백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, USA, 16/750,292 (2020)
백록현,윤준식,이승환,정진수, 금속 소스/드레인 기반 전계효과 트랜지스터 및 이의 제조방법, USA, 16/562,693 (2019)
백록현,윤준식,정진수,이승환, 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0074877 (2019)
백록현,윤준식,정진수,이승환, 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0074877 (2019)
백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0011571 (2018)
백록현,윤준식,정진수,이승환, 펀치스루 스토퍼가 필요 없는 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2019-0011571 (2018)
백록현,윤준식,이승환,정진수, 금속 소스/드레인 기반 전계효과 트랜지스터 및 이의 제조방법, 한국, 10-2018-0114050 (2018)
정윤하,김동원,김대만,백록현,박찬훈,이상현,박수영, 전계 효과 트랜지스터 및 그 제조 방법, 한국, 10-2012-0084943 (2013)
정윤하,김동원,김대만,백록현,박찬훈,이상현,박수영, 나노 와이어 트랜지스터 및 제조 방법, 한국, 10-2012-0043900 (2012)

학회발표

Ultrastacked ForksheetFET and Monolithic ComplementaryFET for Å75 node Visibility Invited , , 0, 0, - (2024)
초고성능 및 초고집적이 가능한 패턴 유전체 절연 벽을 갖춘 2nm 노드 나노시트 전계 효과 트랜지스터 , , 0, 0, - (2024)
Analysis of Mechanical Stress Induced in MultiStack and Number of Wordlines of 3D NAND Flash Memory , , 0, 0, - (2024)
Exploring the Impact of Channel Tapered Angle and Number of Channel Stacks in Nanosheet and Forksheet FETs , , 0, 0, - (2024)
Program Strategy of 3D NAND Flash to Mitigate Threshold Voltage Distribution Widening at CrossTemperature , , 0, 0, - (2024)
8inch MgO Thin Film Technology for NextGeneration Memory Applications , , 0, 0, - (2024)
Holistic Analysis of Asymmetry in Vertical Silicon Gateallaround Nanosheet FETs , , 0, 0, - (2023)
Channel Trimming Process to Improve Electrothermal Characteristics for Sub3nm Node Nanosheet FieldEffect Transistors with Laser Spike Annealing , , 0, 0, - (2023)
Frontside and Backside Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications , , 0, 0, - (2023)
Investigation of SelfHeating Effect in Forksheet FETs for Sub3nm Node, 7th IEEE Electron Devices Technology and Manufacturing Conference Strengthen the Global Semiconductor Research Collaboration After the Covid19 Pandemic EDTM 2023, 0, 0, - (2023)
Forward Body Bias Technique in DRAM Peripheral Transistor at Cryogenic Temperature for Quantum Computing Applications, 7th IEEE Electron Devices Technology and Manufacturing Conference Strengthen the Global Semiconductor Research Collaboration After the Covid19 Pandemic EDTM 2023, 0, 0, - (2023)
Optimization of Ge Mole Fraction in Sacrificial Layers for Sub3nm Node Silicon Nanosheet FETs , , 0, 0, - (2023)
Study of continuouswave RGB laser annealing for the activation of phosphorusborondoped Si deep junction with high scan speed , , 0, 0, - (2023)
Development of MFMIS Gatestack with Thick Hafnium Zirconium Oxide HZO for Nonvolatile Memory Application, 7th IEEE Electron Devices Technology and Manufacturing Conference Strengthen the Global Semiconductor Research Collaboration After the Covid19 Pandemic EDTM 2023, 0, 0, - (2023)
Analysis of Mechanical Stress on Charge Trap Nitride CTN for Program Operation in 3D NAND Flash Memory , , 0, 0, - (2023)
Neural Networkbased Prediction for CrossTemperature Induced VT Distribution Shift of 3D NAND flash memory , , 0, 0, - (2023)
Novel scheme to form nonuniform oxide in gateallaround NCFETs for capacitance matching , , 0, 0, - (2023)
BCl3Cl2 plasma etching process of ferroelectric gate stack for device integration , , 0, 0, - (2023)
Improved ISPP Scheme of 3D NAND Flash for Narrow Threshold Voltage Distribution , , 0, 0, - (2022)
PEALD with Posttreatments for Interface Improvement of HfO2based MetalInsulatorSemiconductor Structures , , 0, 0, - (2022)
Sensitivity Analysis of Each Inner Spacer Thickness Variation in Sub 3nm Node Si Nanosheet FETs , , 0, 0, - (2022)
HighSpeed Ternary CMOS Inverter by Monolithic Integration of NbO2 Threshold Switch with MOSFET, 2021 IEEE International Electron Devices Meeting, 0, 0, - (2021)
Optimal Energetic Trap Distribution of Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using Machine Learning Methodology , , 0, 0, - (2021)
An Analysis on Electrical Characteristics of SubmicronLTPS ThinFilmTransistors, 한국반도체디스플레이기술학회, 0, 0, - (2018)
Effect of Elliptical Channel Shape on Memory Characteristics of Vertical 3D NAND Flash Memory, 한국반도체디스플레이기술학회, 0, 0, - (2018)
Low Frequency Noise in SiC DoubleImplant MOSFETs, 제25회 한국반도체학술대회, 0, 0, - (2018)
Improved Thermal Stability and Lower Sheet Resistance of NiSi with Carbon Presilicidation Implant, 제25회 한국반도체학술대회, 0, 0, - (2018)
New multi frequency capacitance extraction methodology for leaky MOS capacitor with HighK dielectric and metal gate, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
Cryogenic RF Characteristics of HfO2Gated nMOSFET, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
PBTI and HCI stressinduces trap generation in SiO2HfO2 gate stack NMOSFETs and its impact on low frequency noise, INTERNATIONAL SYMPOSIUM ON ADVANCED GATE STACK TECHNOLOGY, 0, 0, - (2008)
RF characteristics for 70 nm MOSFETs below 77K, ASIAPACIFIC WORKSHOP ON FUNDAMENTALS AND APPLICATIONS OF ADVANCED SEMICONDUCTOR DEVICES, 0, 0, - (2007)

연구실적

(민간)5 NM급 이하 차세대 LOGIC 소자 원천요소기술 개발, (사)한국반도체연구조합 (2017-2017)
(정부)5 NM 급 이하 차세대 LOGIC 소자 원천요소기술개발, 산업자원부 (2017-2017)
백록현_신규부임교수 기자재지원(1차_학과), 포항공과대학교 (2017-2018)
백록현_신규부임교수 연구비지원(1차_학과), 포항공과대학교 (2017-2018)
백록현_신규부임교수 기자재지원(1차_대학), 포항공과대학교 (2017-2018)
SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2017-2018)
(정부)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 산업자원부 (2017-2018)
(민간)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2017-2018)
학생인건비통합관리과제, 포항공대산학협력단 (2018-2022)
백록현_신규부임교수 기자재지원(대학_2차), 포항공과대학교 (2018-2019)
백록현_신규부임교수 연구비지원(2차_학과), 포항공과대학교 (2018-2019)
SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2018-2019)
4.14714 이월과제, 재단법인한국연구재단 (2018-2019)
(정부)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 산업자원부 (2018-2018)
(민간)5NM 노드 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2018-2018)
3D NAND FLASH의 APC(ABNORMAL PROGRAM CELL) 원인 인자 규명, 에스케이하이닉스 주식회사 (2018-2020)
SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 한국산업기술기획평가원 (2019-2019)
연구개발과제[2015년 신설], 포항공과대학교 (2019-2030)
4.16222_이월과제, 주식회사 인터로조 (2019-2019)
4.15043_이월과제, 주식회사 인터로조 (2019-2019)
스마트 콘텍트렌즈 플랫폼 기술 개발, 주식회사 인터로조 (2019-2019)
(민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, (사)한국반도체연구조합 (2019-2019)
백록현_신규부임교수 기자재지원(3차_대학), 포항공과대학교 (2019-2020)
백록현_신규부임교수 연구비지원(3차_학과), 포항공과대학교 (2019-2020)
SUB 7NM NODE 향 MULTI-GATE MOSFET 소자 설계, 재단법인한국연구재단 (2019-2020)
SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화 , 한국산업기술기획평가원 (2020-2020)
(민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 재안 및 성능 최적화, (사)한국반도체연구조합 (2020-2020)
AI 기법을 이용한 DRAM PERI. 소자의 공정 및 성능 최적화, 에스케이하이닉스 주식회사 (2020-2021)
3D NAND FLASH의 APC(ABNORMAL PROGRAM CELL)의 원인 인자 규명 , 에스케이하이닉스 주식회사 (2020-2021)
3D-NAND FLASH의 초고난도 산업 난제 해결을 위한 융합형 메모리 AI 플랫폼 개발, 재단법인한국연구재단 (2020-2021)
기초연구실 부서운영비, 포항공대산학협력단 (2020-2021)
신소자 및 CMOS 동시 집적을 위한 8인치 공정 플랫폼 개발, 재단법인한국연구재단 (2020-2020)
신소자 및 CMOS동시 집적을 위한 8인치 공정 플랫폼 개발, 재단법인한국연구재단 (2021-2021)
4.0020639_이월과제, 재단법인한국연구재단 (2021-2021)
SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 제안 및 성능 최적화, 한국산업기술기획평가원 (2021-2021)
(민간)SUB 5NM 노드 향 GATE-ALL-AROUND 소자와 TSV를 이용한 3DIC 구조 재안 및 성능 최적화, (사)한국반도체연구조합 (2021-2021)
3D-NAND FLASH의 초고난도 산업 난제 해결을 위한 융합형 메모리 AI 플랫폼 개발, 재단법인한국연구재단 (2021-2022)
4.0020563_이월과제, 재단법인한국연구재단 (2021-2022)
AI를 이용한 트랜지스터 최적화 및 분석 능률 극대화 방안, 에스케이하이닉스 주식회사 (2021-2022)
신소자 및 CMOS동시 집적을 위한 8인치 공정 플랫폼 개발, 재단법인한국연구재단 (2022-2023)
4.0021076/4.21984_이월과제, 재단법인한국연구재단 (2022-2023)
수직형 SIGE 채널 GAA 소자와 고성능/고집적 모놀리식 3차원 집적회로의 통합 설계를 위한 핵심 기반기술 개발, 재단법인한국연구재단 (2022-2023)
3D-NAND FLASH의 초고난도 산업 난제 해결을 위한 융합형 메모리 AI 플랫폼 개발, 재단법인한국연구재단 (2022-2023)
4.0022427/4.0022946_이월과제, 재단법인한국연구재단 (2022-2023)
차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, 한국산업기술기획평가원 (2022-2022)
3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, 한국산업기술기획평가원 (2022-2022)
(민간)차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, (사)한국반도체연구조합 (2022-2022)
(민간)3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, (사)한국반도체연구조합 (2022-2022)
RTS와 FPN 개선을 위한 TRAP 특성 분석 및 MOSFET 구조 제안 , 삼성전자(주) (2022-2023)
4.0024925_이월과제, (사)한국반도체연구조합 (2023-2023)
4.0024924_이월과제, (사)한국반도체연구조합 (2023-2023)
4.24771_이월과제, 한국산업기술기획평가원 (2023-2023)
4.24772_이월과제, 한국산업기술기획평가원 (2023-2023)
차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, 한국산업기술기획평가원 (2023-2023)
3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, 한국산업기술기획평가원 (2023-2023)
3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, (사)한국반도체연구조합 (2023-2023)
(민간)차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, (사)한국반도체연구조합 (2023-2023)
AI기반 초고집적 차세대 3D-NAND FLASH 개발, 포항공과대학교 (2023-2024)
수직형 SIGE 채널 GAA 소자와 고성능/고집적 모놀리식 3차원 집적회로의 통합 설계를 위한 핵심 기반기술 개발, 재단법인한국연구재단 (2023-2024)
4.0023975_이월과제, 재단법인한국연구재단 (2023-2024)
3파장 레이저의 선택적 어닐링을 통한 3NM 노드 이하 3DIC 로직 집적공정용 핵심요소기술 개발, 한국산업기술기획평가원 (2023-2023)
초고층 3D NAND 메모리를 위한 고이동도 채널/유전막 신소재 개발 및 AI 기반 대규모 해석 플랫폼 구축, 한국산업기술기획평가원 (2023-2023)
(민간)초고층 3D NAND 메모리를 위한 고이동도 채널/유전막 신소재 개발 및 AI 기반 대규모 해석 플랫폼 구축 , (사)한국반도체연구조합 (2023-2023)
(민간)3파장 레이저의 선택적 어닐링을 통한 3NM 노드 이하 3DIC 로직 집적공정용 핵심요소기술 개발, (사)한국반도체연구조합 (2023-2023)
LOGIC 및 HIGH VPP용 FINFET 소자의 성능 및 신뢰성 최적화, 에스케이하이닉스 주식회사 (2024-2024)
4.0027265_이월과제, (사)한국반도체연구조합 (2024-2024)
(민간) 차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, (사)한국반도체연구조합 (2024-2024)
(민간)3파장 레이저의 선택적 어닐링을 통한 3NM 노드 이하 3DIC 로직 집적공정용 핵심요소기술 개발, (사)한국반도체연구조합 (2024-2024)
4.0027266_이월과제, (사)한국반도체연구조합 (2024-2024)
4.0026534/4.0025349_이월과제, (사)한국반도체연구조합 (2024-2024)
4.0026535/4.0025371_이월과제, (사)한국반도체연구조합 (2024-2024)
초고층 3D NAND 메모리를 위한 고이동도 채널/유전막 신소재 개발 및 AI 기반 대규모 해석 플랫폼 구축, 한국산업기술기획평가원 (2024-2024)
3파장 레이저의 선택적 어닐링을 통한 3NM 노드 이하 3DIC 로직 집적공정용 핵심요소기술 개발, 한국산업기술기획평가원 (2024-2024)
4.26917_이월과제, 한국산업기술기획평가원 (2024-2024)
차세대 반도체 소자 성능 목표치를 실시간으로 구현 가능한 AI 기반 통합 TDA 플랫폼 기술, 한국산업기술기획평가원 (2024-2024)
3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, 한국산업기술기획평가원 (2024-2024)
4.26531/4.26567_이월과제, 한국산업기술기획평가원 (2024-2024)
4.26915_이월과제, 한국산업기술기획평가원 (2024-2024)
4.26530/4.26569_이월과제, 한국산업기술기획평가원 (2024-2024)
[민간]3NM 이하급 공정기술 구현을 위한 고유전율 게이트 절연막, 저저항 소스/드레인, 신규 채널 소재와 신규 소자구조 연구, (사)한국반도체연구조합 (2024-2024)
(민간)초고층 3D NAND 메모리를 위한 고이동도 채널/유전막 신소재 개발 및 AI 기반 대규모 해석 플랫폼 구축, (사)한국반도체연구조합 (2024-2024)
수직형 SIGE 채널 GAA 소자와 고성능/고집적 모놀리식 3차원 집적회로의 통합 설계를 위한 핵심 기반기술 개발, 재단법인한국연구재단 (2024-2025)
4.0025587_이월과제, 재단법인한국연구재단 (2024-2025)
4.0028645_이월과제, (사)한국반도체연구조합 (2025-2025)