POSTECH CSDL Wins 2nd Place at the MLCAD 2025 Contest

The CAD & SoC Design Laboratory (CSDL) of POSTECH, led by Prof. Seokhyeong Kang, placed second overall in the MLCAD 2025 Contest,— ReSynthAI: Physical-Aware Logic Resynthesis for Timing Optimization Using AI, co-organized by Arizona State University (ASU) and NVIDIA.

The contest was held as part of the 7th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD 2025), which took place in Santa Cruz, California, USA. 

A Global Competition
This year’s contest attracted 27 research teams from leading universities and companies worldwide, including IMEC, NXP, Samsung, UT Austin, Texas A&M, UC Davis, CUHK, and Fudan University. POSTECH CSDL competed as Team 13 (CSDL) among participants from top institutions.

Contest Theme & Tasks
The 2025 challenge, ReSynthAI: Physical-Aware Logic Resynthesis for Timing Optimization, focused on physical-aware logic resynthesis for timing optimization after global routing. Teams were asked to apply AI methods—supervised, unsupervised, and reinforcement learning—to perform netlist-level optimizations such as gate sizing, buffer insertion, Vt swaps, gate cloning, and logic restructuring, all while ensuring routability and minimizing congestion.

Final Results
1st Place: Fudan University (764 points)
2nd Place: POSTECH (713 points)
3rd Place: NXP (482 points)

POSTECH CSDL excelled by ranking first in 5 out of the 12 benchmarks, demonstrating competitiveness nearly equal to Fudan University. Despite a narrow point margin in the final tally, the team secured an outstanding second place overall.

Significance
This performance highlights POSTECH CSDL’s world-class expertise in AI-driven semiconductor design automation. By showcasing innovative approaches to physical-aware optimization, the lab has reaffirmed its role as a leader in bridging AI and EDA. Looking ahead, CSDL will continue to pursue research that advances both academic excellence and industrial innovation at the forefront of AI and semiconductor design.